The present invention relates, in general, to a method and structure for bonding integrated circuit chips and, more particularly, to fluxless flip-chip bonding processes.
An increasingly important aspect of manufacturing an integrated circuit chip, also referred to as an integrated circuit die, is mounting the integrated circuit chip to a substrate. Often times, the goal of this task is to provide the chip with as many input/output ("I/O") terminals as possible. Flip-chip bonding is one of various surface mounting techniques which have been developed in an effort to provide high density area interconnections between the chip and the substrate.
In the flip-chip bonding process, the die is mounted directly to the substrate. Generally, the flip-chip process entails disposing a plurality of solder bumps on the upper-surface of the die, flipping the die and mating these solder bumps with corresponding bonding pads located on the substrate, and then heating the die and the substrate so as to reflow the solder bumps. Once reflowed each bump forms a bond between the die and the substrate, which functions as both an electrical and physical contact.
However, previously known flip-chip bonding processes suffer from various drawbacks. For example, the controlled collapse chip connection ("C4") flip-chip bonding process utilizes solder bumps comprising a lead-tin alloy, which require an activating agent, such as flux, to reduce the oxides which form on the surface of the bump. The oxides must be removed if an adequate bond between the die and the substrate is to be obtained. However, the use of flux leaves a residue, which must be removed in order to prevent corrosion problems. Such cleaning is a difficult process to accomplish, and adds both time and cost to the manufacturing process. Furthermore, the use of the lead-tin alloy is often unsatisfactory because of its tendency to fracture due to thermal stress. The C4 flip-chip bonding process also exhibits surface tension between the solder bump and the bonding pad, which disadvantageously functions to limit the minimum allowable pitch (i.e., distance between solder bumps).
Another drawback associated with the C4 process is that for proper operation the minimum allowable size of the solder bumps range from 3-5 mils. Notwithstanding the fact that the size of the solder bumps cannot be further reduced (a further reduction would allow more bumps per area), since the entire solder bump becomes liquid during the bonding process, the substantial size of the bump increases the probability of a bump forming a short circuit with one or more adjacent bumps during the bonding process.
Another known flip-chip bonding process can be referred to as the indium-bump process. In this process, the solder bump comprising indium formed on the die is brought into contact with the bonding pad on the substrate, and then heated so as to cause the solder bump to reflow and form a solder column. While, this process does not rely on surface tension to assist in the alignment process, the materials utilized for the solder bumps still require the use of flux to remove the oxides prior to the reflow process. As such, the indium-bump process suffers from the same drawbacks as set forth above. In addition, as indium melts at 120 C, once the reflow process is completed, further high temperature operations are prohibited. Furthermore, the indium column which bonds the die to the substrate is a relatively low strength structure. As such, the bond is susceptible to fractures resulting from forces applied during subsequent processing techniques and/or during normal operating conditions.
Another known flip-chip process is gold thermal compression bonding. According to this process, a gold bump formed on the die is brought into contact with a gold bonding pad disposed on the substrate. The gold bump and the gold bonding pad are then joined by heating the structure while simultaneously pressing the bump and pad together. However, when attempting to bond a die having on the order of 1000 solder bumps, this technique is inadequate due to the fact that machines capable of exerting the necessary compression force are commercially unavailable.
Another disadvantage with this process is that large deformations of the bump are required to generate an acceptable bond. Typically, the force applied must be sufficient to deform approximately 30% of the bump. Application of such force can result in undesirable piezoelectric effects when applied to a substrate already containing circuit elements, as well as result in short circuits with adjacent bumps.
It has also been known to use gold bumps having either a layer of tin, or possibly indium, disposed thereon in the flip-chip bonding process. Specifically, a gold bump comprising tin disposed on the die is brought into contact with a gold bonding pad disposed on the substrate. The structure is then subjected to a reflow process such that the tin and the gold form an intermetallic compound which functions as a bond between the die and the substrate. However, disadvantageously, this technique requires the use of a flux, and therefore suffers from the associated problems. In addition, the use of tin results in an unreliable contact, as tin forms open circuits over time.
In addition to the aforementioned problems, except for the C4 process, none of the foregoing flip-chip bonding processes allow for the formation of a hermetic seal surrounding the integrated circuit die simultaneously with the bonding of the die to the substrate. This results from the need to remove the flux from the bonds formed during the flip-chip bonding process. However, while the C4 process allows the generation of a hermetic seal, the seal formed is too large, typically on the order of 250 microns.
Accordingly, there is a need for a flip-chip bonding process for bonding a die having bumps (i.e., I/O ports) ranging in number from 1 to over 1000 that is inexpensive, that does not require the use of a flux, that does not require excessive compression forces, that minimizes reliability problems, such as those associated with the use of tin, and that allows for the formation of a hermetic seal which surrounds each individual integrated circuit die.